US 10,418,277 B2Granted

Air gap spacer formation for nano-scale semiconductor devices

AssigneeInternational Business Machines Corporation

InventorsKangguo Cheng, Thomas J. Haigh, Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen, Chanro Park, Tenko Yamashita

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Claims20

Dependent claims

A method, comprising:

forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures;
etching the insulating material to form a space between the first and second metallic structures;
and
depositing a layer of dielectric material over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;
wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure;
wherein depositing the layer of dielectric material over the first and second metallic structures comprises:
depositing a non-conformal layer of dielectric material to form a dielectric capping layer having a pinch-off region that is aligned to the space between the first and second metallic structures;
wherein the pinch-off region is formed in the dielectric capping layer above the upper surface of the at least one first metallic structure and second metallic structure;
and
wherein depositing the layer of dielectric material comprises depositing a non-conformal layer of silicon carbon nitride material using a plasma-enhanced chemical vapor deposition process, wherein parameters of the plasma-enhanced chemical vapor deposition process comprise (i) a gas environment comprising trimethyl silane at a flow rate in a range of 200-500 standard cubic centimeter per minute and ammonia at a flow rate in a range of 300-800 standard cubic centimeter per minute, (ii) RF power in a range of 300-600 watts, (iii) pressure in a range of 2-6 Torr, and (iv) a deposition rate in a range of 0.5-5 nanometers/second.

7 more elements

A method, comprising:

forming a fin field-effect transistor device on a substrate, the fin field-effect transistor device comprising a vertical semiconductor fin, a metallic gate structure formed over a portion of the vertical semiconductor fin, a gate encapsulation layer covering upper and sidewall surfaces of the metallic gate structure, and first and second source/drain contacts formed in contact with portions of the vertical semiconductor fin extending from the sidewall surfaces of the metallic gate structure, wherein gate encapsulation layer comprises gate sidewall spacers disposed between the metallic gate structure and the first and second source/drain contacts and a gate capping layer disposed over the upper surface of the metallic gate structure;
etching the gate encapsulation layer to form spaces between the metallic gate structure and the first and second source/drain contacts;
and
depositing a layer of dielectric material over the fin field-effect transistor device to thereby cover the upper surface of the metallic gate structure with the dielectric material and form air gaps in the spaces between the metallic gate structure and the first and second source/drain contacts;
wherein upper portions of the air gaps are disposed above the upper surface of the metallic gate structure and disposed below upper surfaces of the first and second source/drain contacts;
and
wherein bottom portions of the air gaps are disposed below bottom surfaces of the first and second source/drain contacts.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/977,437Filed 11 May 2018 · continuation
Priority: 9 Aug 2016
Published: US 2018/0047615 A113 Sep 2018
Granted: 17 Sep 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10W 20/46
Characterised by their insulating parts: comprising air gaps
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers

Family

Application15/232,341Parent of this division · filed 9 Aug 2016
Application15/789,416Parent of this continuation · filed 20 Oct 2017
US 9,892,961 B1Parent of this division · filed 13 Feb 2018
US 2018/0261494 A1Pre-grant publication · published 13 Sep 2018
Application15/789,416Parent of this division
US 10,115,629 B2Related patent
US 2018/0047615 A1Published application
US 2018/0047617 A1Published application
US 10,418,277 B2This patent

From the US filing history. Foreign family members aren’t listed.