Low power analog vector-matrix multiplier

An analog matrix multiplier, comprising:

• a plurality of successive approximation registers (SAR) operating in parallel, each successive approximation register (SAR) having an SAR digital output;
• a plurality of scaling and recombining circuits for scaling and recombining each SAR's digital output, each SAR digital output resulting from quantization of a bit-wise multiplication of a digital weight matrix with an input analog voltage vector, each scaling and recombining circuit connected in series to a successive approximation register (SAR) of the plurality of successive approximation registers (SAR);
• and
• a plurality of charge transfer circuits, each charge transfer circuit connected in series to a successive approximation register (SAR) of the plurality of successive approximation registers (SAR).