Pipelined cascaded digital signal processing structures and methods
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
Estimating the term…
Abstract
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
Claims15
Circuitry accepting a data input and generating a data output based on said data input, said circuitry comprising:
- a first circuit block, including:
- a first multiplier circuit,
- a first plurality of pipeline registers that pipeline an operation of the first multiplier circuit,
- a plurality of balancing registers that are disposed to balance the first plurality of pipeline registers,
- a first adder circuit accepting a first adder input from within the first circuit block and a second adder input from a first interblock connection,
- a first selectable connection between one or more registers from the plurality of balancing registers and a register of the first plurality of the pipeline registers such that the one or more registers are configurable to be re-used as latency registers to create additional latency for the first adder input;
- a second circuit block cascaded to the first circuit block via the first interblock connection, including:
- a second multiplier circuit,
- a second plurality of pipeline registers that pipeline an operation of the second multiplier circuit, wherein the second plurality of pipeline registers has a second selectable connection such that one or more of the second plurality of pipeline registers are selectively bypassed;
- and
- system processing circuitry configured to balance the first adder input and the second adder input by selecting the first selectable connection or the second selectable connection.
A method for operating circuitry that includes first and second circuit blocks having respective first and second multiplier circuits and respective first and second adder circuits, and wherein the second circuit block is cascaded to the first circuit block via an interblock connection, comprising:
- receiving a first data signal at a first plurality of pipeline registers in the first circuit block, wherein the first plurality of pipeline registers pipeline an operation of the first multiplier circuit;
- transmitting the first data signal through the first plurality of pipeline registers to a first adder input of the first adder circuit;
- receiving a second data signal at a second plurality of pipeline registers in the second circuit block, wherein the second plurality of pipeline registers pipeline an operation of the second multiplier circuit;
- transmitting the second data signal through the second plurality of pipeline registers and the interblock connection to a second adder input of the first adder circuit;
- configuring a selectable connection coupled between the first multiplier circuit and the first adder input in the first circuit block to select an output of the first multiplier circuit as the first data signal;
- and
- configuring a second selectable connection coupled between one or more registers, from a plurality of balancing registers in the first circuit block that are disposed to balance the first plurality of pipeline registers, and a register of the first plurality of the pipeline registers such that the one or more registers are re-used as latency registers to create additional latency for the first adder input.
An integrated circuit, comprising:
- first, second, and third DSP blocks that each comprise a multiplier circuit, an adder circuit, and a plurality of pipeline registers that pipeline an operation of the multiplier circuit, wherein:
- a first interblock connection couples the first and the second DSP blocks;
- a second interblock connection couples the second and the third DSP blocks;
- and
- the adder circuit in the first DSP block accepts a first adder input from within the first DSP block and a second adder input from the first interblock connection;
- and
- a selectable connection coupled between one more registers from a plurality of balancing registers in the first DSP block that are disposed to balance the plurality of pipeline registers in the first DSP block and a register of the plurality of the pipeline registers in the first DSP block such that the one or more registers are re-used as latency registers to create additional latency for the first adder input;
- and
- system processing circuitry configured to balance the first and second adder inputs by selecting the selectable connection.
Dependencies are inferred from the claim text.