Timing optimizations in circuit designs using opposite clock edge triggered flip-flops

A system for implementing a circuit design, comprising:

• a memory configured to store program code;
• and
• a processor coupled to the memory, wherein the processor, in response to executing the program code, is configured to initiate operations including:
• detecting a net of the circuit design with a hold timing violation;
• generating a list including each load of the net;
• filtering the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing;
• and
• modifying the circuit design by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point;
• wherein the clock signal used to clock the inserted flip-flop is the clock signal having a higher frequency from among the clock signal of the start point and the clock signal of the end point.

A computer program product for implementing a circuit design, comprising:

• a computer readable storage medium having program code stored thereon, wherein the program code is executable by computer hardware to initiate operations including:
• detecting a net of the circuit design with a hold timing violation;
• generating a list including each load of the net;
• filtering the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing;
• and
• modifying the circuit design by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point;
• wherein the clock signal used to clock the inserted flip-flop is the clock signal having a higher frequency from among the clock signal of the start point and the clock signal of the end point.