High throughput hardware unit providing efficient lossless data compression in convolution neural networks
AssigneeAmbarella, Inc.
InventorsJunqiang Lan, Zhijian Lu
Life of this patent
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Abstract
An apparatus includes a first memory interface circuit, a second memory interface circuit, and a compression circuit coupled between the first memory interface circuit and the second memory interface circuit. The compression circuit may be configured to receive a coding block of data via the first memory interface circuit, generate a reduced size representation of the coding block, and write the reduced size representation of the coding block to an external memory using the second memory interface circuit. The reduced size representation of said coding block generally comprises a first bit map, a second bit map, and zero or more non-zero values.
Claims20
An apparatus comprising:
- a first memory interface circuit;
- a second memory interface circuit;
- and
- a compression circuit coupled between said first memory interface circuit and said second memory interface circuit, wherein said compression circuit is configured to (i) receive a coding block of data via said first memory interface circuit, (ii) generate a reduced size representation of the coding block comprising a first bit map, a second bit map, and zero or more non-zero values, and (iii) write the reduced size representation of the coding block to an external memory using said second memory interface circuit.
A method of generating a data structure providing lossless data compression of blocks of data of one or more intermediate layers of a convolutional neural network layer, said method comprising:
- creating a first bit map identifying each element in a coding block of data as a zero or non-zero value;
- reordering any non-zero elements into a plurality of bit planes;
- reducing a magnitude of said non-zero elements by a predetermined amount;
- creating a second bit map identifying each element in said plurality of bit planes as a zero or non-zero value;
- and
- concatenating said first bit map, said second bit map, and any remaining bit plane non-zero values.
Dependencies are inferred from the claim text.