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US 10,411,677 B2Granted
Flip-flop including 3-state inverter
AssigneeSamsung Electronics Co., Ltd.
InventorsHa-Young Kim, Dalhee Lee, Hyoung-Suk Oh, Keunho Lee, Taejoong Song, Sungwe Cho
Life of this patent
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Abstract
A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
Claims20
A flip-flop comprising:
- an input interface configured to receive a first signal, and output the received first signal as a second signal in synchronization with a clock;
- a first latch comprising a first inverter and a second inverter, and configured to store the second signal output from the input interface in synchronization with the clock;
- a third inverter configured to output the second signal stored in the first latch as a third signal in synchronization with the clock;
- and
- a second latch comprising a fourth inverter and a fifth inverter, and configured to store the third signal output from the third inverter in synchronization with the clock,
- wherein the third inverter and the fifth inverter comprise:
- first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins;
- and
- second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
6 more elements
A flip-flop comprising:
- an input interface configured to receive a first signal, and output the received first signal as a second signal in synchronization with a clock;
- a first latch comprising a first inverter and a second inverter, and configured to store the second signal output from the input interface in synchronization with the clock;
- a third inverter configured to output the second signal stored in the first inverter as a third signal in synchronization with the clock;
- a second latch comprising a fourth inverter and a fifth inverter, and configured to store the third signal output from the third inverter in synchronization with the clock;
- and
- a sixth inverter configured to invert the third signal and output the inverted third signal as a fourth signal,
- wherein the third inverter includes first and second P-type metal-oxide-semiconductor (PMOS) transistors and first and second N-type metal-oxide-semiconductor (NMOS) transistors,
- wherein the fifth inverter includes third and fourth PMOS transistors and third and fourth NMOS transistors,
- wherein the first to fourth PMOS transistors are disposed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins;
- and
- wherein the first to fourth NMOS transistors are disposed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
8 more elements
Dependencies are inferred from the claim text.