Six-transistor (6T) SRAM cell structure

A 6T SRAM cell, comprising:

• a first doped contiguous active region in a semiconductor substrate;
• a second doped contiguous active region in the semiconductor substrate adjacent to the first doped contiguous active region;
• a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which has a bottom source/drain region formed in said first doped contiguous active region, wherein said first N-type pull-down transistor is positioned laterally between said first N-type pass gate transistor and said first P-type pull-up transistor;
• a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which has a bottom source/drain region formed in said second doped contiguous active region, wherein said second N-type pull-down transistor is positioned laterally between said second N-type pass gate transistor and said second P-type pull-up transistor, wherein said first N-type pass gate transistor, said first N-type pull-down transistor and said first P-type pull-up transistor on said first doped contiguous active region are positioned opposite, respectively, said second P-type pull-up transistor, said second N-type pull-down transistor and said second N-type pass gate transistor on said second doped contiguous active region.

A 6T SRAM cell, comprising:

• a first doped contiguous active region in a semiconductor substrate;
• a second doped contiguous active region in the semiconductor substrate adjacent to the first doped contiguous active region;
• a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which has a bottom source/drain region formed in said first doped contiguous active region, wherein said first N-type pull-down transistor is positioned laterally between said first N-type pass gate transistor and said first P-type pull-up transistor;
• a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which has a bottom source/drain region formed in said second doped contiguous active region, wherein said second N-type pull-down transistor is positioned laterally between said second N-type pass gate transistor and said second P-type pull-up transistor, wherein said first N-type pass gate transistor, said first N-type pull-down transistor and said first P-type pull-up transistor on said first doped contiguous active region are positioned opposite, respectively, said second P-type pull-up transistor, said second N-type pull-down transistor and said second N-type pass gate transistor on said second doped contiguous active region;
• a first N-doped shared source/drain region in said first doped contiguous active region that is shared by said bottom source/drain regions of said first N-type pass gate transistor and said first N-type pull-down transistor;
• a first shared gate structure that is shared by said first N-type pull-down transistor and said first P-type pull-up transistor;
• a second N-doped shared source/drain region in said second doped contiguous active region that is shared by said second bottom source/drain regions of said N-type pass gate transistor and said second N-type pull-down transistor;
• a second shared gate structure that is shared by said second N-type pull-down transistor and said second P-type pull-up transistor;
• a first gate-to-source/drain (GSD) contact structure that conductively couples said first shared N-doped source/drain region with said second shared gate structure;
• and
• a second gate-to-source/drain (GSD) contact structure that conductively couples said second shared N-doped source/drain region with said first shared gate structure.