Current-controlled CMOS logic family
AssigneeAvago Technologies International Sales Pte. Limited
InventorArmond Hairapetian
Life of this patent
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Abstract
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
Claims17
An apparatus comprising:
- an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
- CMOS circuitry, within the integrated circuitry, configured to:
- receive a plurality of signals;
- and
- process the plurality of signals to generate another plurality of signals;
- and
- CMOS circuitry, within the integrated circuitry, configured to:
- receive the another plurality of signals from the CMOS circuitry;
- and
- process the another plurality of signals to generate a signal.
An apparatus comprising:
- an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
- CMOS circuitry, within the integrated circuitry, configured to:
- receive a signal;
- and
- process the signal to generate a plurality of signals;
- and
- CMOS circuitry, within the integrated circuitry, configured to:
- receive the plurality of signals from the CMOS circuitry;
- process the plurality of signals to generate another plurality of signals;
- and
- output the plurality of signals.
An apparatus comprising:
- an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
- CMOS circuitry, within the integrated circuitry, configured to:
- receive a signal;
- process the signal to generate a first plurality of signals;
- first CMOS circuitry, within the integrated circuitry, configured to:
- receive a first of the first plurality of signals from the CMOS circuitry;
- process the first of the first plurality of signals to generate a first of a second plurality of signals;
- and
- output the first of the second plurality of signals;
- and
- second CMOS circuitry, within the integrated circuit circuitry, configured to:
- receive a second of the first plurality of signals from the CMOS circuitry;
- process the second of the plurality of signals to generate a second of the second plurality of signals;
- and
- output the second of the second plurality of signals.
Dependencies are inferred from the claim text.