Pseudo static random access memory and refresh method thereof
AssigneeWinbond Electronics Corp.
InventorYuji Nakaoka
Life of this patent
Estimating the term…
Abstract
A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.
Claims15
A refresh method for a pseudo static random access memory (SRAM), comprising:
- providing a basic clock signal;
- at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal;
- at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal;
- and
- receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.
A pseudo SRAM comprising:
- a refresh signal generator, generating a refresh request signal;
- a controller, coupled to the refresh signal generator;
- a dynamic memory array, coupled to the controller;
- and
- an input/output circuit, coupled to the dynamic memory array and the controller,
- wherein the controller is configured to:
- receive a basic clock signal;
- receive a chip enable signal enabled at a first time point to perform a first write operation, and receive write data during an enabled time period of the chip enable signal;
- at a delay time point after the first time point, enable a sub-word line driving signal, and write the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal;
- and
- receive the refresh request signal, and determine whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.
Dependencies are inferred from the claim text.