Memory operation encryption

In an electronic device comprising a processing module coupled to a memory module via a dedicated interconnect, a method comprising:

• in response to initiation of a load operation:
• encrypting, at a first interface to the interconnect at the processing module, a memory address associated with the load operation using a first key and a first feedback-based cryptologic process to generate an encrypted memory address, the memory address corresponding to a memory location of the memory module, the memory module comprising a plurality of memory locations;
• transmitting the encrypted memory address to the memory module via the interconnect;
• decrypting, at a second interface to the interconnect at the memory module, the encrypted memory address using a second key to obtain a copy of the memory address;
• accessing, at the second interface, a first encrypted data from a memory location of the memory module based on the copy of the memory address;
• encrypting, at the second interface, the first encrypted data using a third key and a second feedback-based cryptologic process to generate a second encrypted data;
• transmitting the second encrypted data from the second interface to the first interface via the interconnect;
• and
• decrypting, at the first interface, the second encrypted data using a fourth key and a third feedback-based cryptologic process to obtain a copy of the first encrypted data.

A processing system comprising:

• a processing module including:
• at least one processor core;
• a first interface coupled to the at least one processor core and coupleable to an interconnect, the first interface comprising:
• a first cryptologic engine to encrypt a representation of store data of a store operation and a memory address associated with the store data using a first key and a first feedback-based cryptologic process to generate first encrypted data and an encrypted memory address, the memory address corresponding to a memory location of a memory module, the memory module comprising a plurality of memory locations;
• and
• wherein the first interface is to transmit the first encrypted data and the encrypted memory address to the memory module via the interconnect.