Continuous time pre-cursor and post-cursor compensation circuits

An intersymbol interference (ISI) compensation circuit for performing pre-cursor and post-cursor compensation on a differential input signal, the ISI compensation circuit comprising:

• a post-cursor compensation circuit configured to perform post-cursor compensation on the differential input signal;
• and
• a pre-cursor compensation circuit configured to perform pre-cursor compensation on the differential input signal, the pre-cursor compensation circuit comprising:
• a differential input configured to receive the differential input signal;
• a differential output configured to provide a pre-cursor compensated version of the differential input signal;
• a first differential pair of transistors comprising first gate terminals coupled to the differential input, first source terminals coupled across a degeneration resistance, and first drain terminals coupled to the differential output;
• and
• a second differential pair of transistors comprising second gate terminals coupled to the differential input, second source terminals coupled across a degeneration capacitance, and second drain terminals coupled to the differential output.

A line card configured to receive a differential input signal via traces on a backplane, the line card comprising:

• a transceiver;
• and
• a backplane connector configured to couple the transceiver to the traces on the backplane to provide the differential input signal to the transceiver for processing,
• wherein the transceiver comprises a pre-cursor compensation circuit configured to perform pre-cursor compensation on the differential input signal, the pre-cursor compensation circuit comprising:
• a differential input configured to receive the differential input signal;
• a differential output configured to provide a pre-cursor compensated version of the differential input signal;
• a first differential pair of transistors comprising first gate terminals coupled to the differential input, first source terminals coupled across a degeneration resistance, and first drain terminals coupled to the differential output;
• and
• a second differential pair of transistors comprising second gate terminals coupled to the differential input, second source terminals coupled across a degeneration capacitance, and second drain terminals coupled to the differential output.