Optimizing clock/data recovery power while maintaining link stability in source synchronous applications

An apparatus, comprising:

• a data transfer system comprising a master, a slave, and a link coupling the master and the slave;
• and
• a CDR (clock/data recovery) profile generator configured to generate a CDR profile of the link,
• wherein the CDR profile comprises one or more noise profiles, each noise profile comprising one or more profile entries, each profile entry including a CDR_ON time and a corresponding eye opening result,
• wherein the CDR_ON time specifies a duration of a CDR_PERIOD in which a CDR circuit of the data transfer system is active, and
• wherein the data transfer system is configured to periodically activate and deactivate the CDR circuit based on the CDR profile to prevent an eye shift/collapse when transferring data between the master and the slave.

A data transfer system, comprising:

• a master, a slave, a link coupling the master and the slave, and a memory configured to store a CDR (clock/data recovery) profile,
• wherein the data transfer system is configured to periodically activate and deactivate a CDR circuit of the data transfer system based on the CDR profile to prevent an eye shift/collapse when transferring data between the master and the slave, and
• wherein the CDR profile stored in the memory is generated by a CDR profile generator,
• wherein the CDR profile comprises one or more noise profiles, each noise profile comprising one or more profile entries, and each profile entry including a CDR_ON time and a corresponding eye opening result, and
• wherein the CDR_ON time specifying a duration of a CDR_PERIOD in which the CDR circuit of the data transfer system is active.

An apparatus, comprising:

• means for generating a CDR (clock/data recovery) profile of a high-speed SERDES (serializer/deserializer) link coupling a master and a slave of a data transfer system;
• and
• means for periodically activating and deactivating a CDR circuit of the data transfer system based on the CDR profile to prevent an eye shift/collapse when transferring data between the master and the slave,
• wherein the CDR profile comprises one or more noise profiles, each noise profile comprising one or more profile entries, each profile entry including a CDR_ON time and a corresponding eye opening result, and
• wherein the CDR_ON time specifies a duration of a CDR_PERIOD in which the CDR circuit is active.