Encoder device, decoder device and transmission apparatus

A decoder device that operates in either a standard speed mode or a K-times speed mode where K is an integer larger than or equal to 2, and that performs error-correction decoding on plural reception frames, each reception frame having a format of a received value arrangement in row and column directions, the decoder device comprising:

• an interleaver circuit configured to, when a single series of plural reception frames is input in the standard speed mode, perform a first interleaving operation to rearrange an order of received value sequences of the single series of reception frames, thereby to output a single series of received value sequences, and configured to, when K series of reception frames into which the single series of plural reception frames is divided are input in the K-times speed mode, perform a second interleaving operation to rearrange an order of received value sequences of the K series of reception frames, thereby to output K series of received value sequences in parallel;
• a group of decoding circuits configured to perform error-correction decoding on either the single series of received value sequences or the K series of received value sequences;
• and
• a deinterleaver circuit configured to perform a deinterleaving operation on output sequences outputted from the group of decoding circuits,
• wherein the interleaver circuit generates, in the standard speed mode, the single series of received value sequences on a basis of received values in plural columns that are arranged at an interval of C columns in the single series of reception frames where C is an integral multiple of K, and generates, in the K-times speed mode, each of the K series of received value sequences on a basis of received values in plural columns that are arranged at an interval of C/K columns in each of the K series of reception frames.