Time domain A/D converter group and sensor device using the same

A time domain analog-to-digital (A/D) converter group comprising:

• a plurality of delay locked loop circuits for dividing a cycle of a master clock that supplies a clock to an entire integrated circuit and outputting a multiphase clock with different timings;
• a logic circuit for synthesizing a plurality of clocks corresponding to gray code from the multiphase clock;
• a plurality of comparators for comparing an input signal and a reference voltage;
• a plurality of internal A/D converters for obtaining A/D conversion values from a comparison output signals from the plurality of comparators;
• and
• a gating circuit for gating the plurality of clocks by a gating control signal,
• wherein the plurality of internal A/D converters perform A/D conversion using the multiphase clock, and
• wherein the gating is performed on a clock corresponding to a least significant bit (LSB) when a level of the input signal is low and a target bit is sequentially increased to a most significant bit (MSB) side when the level of the input signal increases.

A time domain analog-to-digital (A/D) converter group comprising:

• a plurality of delay locked loop circuits for dividing a cycle of a master clock that supplies a clock to an entire integrated circuit and outputting a multiphase clock with different timings;
• a logic circuit for synthesizing a plurality of clocks corresponding to gray code from the multiphase clock;
• a plurality of comparators for comparing an input signal and a reference voltage;
• a plurality of internal A/D converters for obtaining A/D conversion values from comparison output signals from the plurality of comparators;
• and
• a gating circuit for gating the plurality of clocks by a gating control signal,
• wherein the plurality of internal A/D converters perform A/D conversion using the multiphase clock, and
• wherein the gating control signal is generated when a number of clocks from a start of A/D conversion is measured and reached a predetermined number of times.

A time domain analog-to-digital (A/D) converter group comprising:

• a plurality of delay locked loop circuits for dividing a cycle of a master clock that supplies a clock to an entire integrated circuit and outputting a multiphase clock with different timings;
• a logic circuit for synthesizing a plurality of clocks corresponding to gray code from the multiphase clock;
• a plurality of comparators for comparing an input signal and a reference voltage;
• a plurality of internal A/D converters for obtaining A/D conversion values from a comparison output signals from the plurality of comparators;
• and
• a gating circuit for gating the plurality of clocks by a gating control signal,
• wherein the plurality of internal A/D converters perform A/D conversion using the multiphase clock, and
• wherein the gating control signal is generated when the input signal of a D/A converter which generates the reference voltage reaches a predetermined value.