On-chip calibration circuit and method with half-step resolution

A calibration circuit comprising:

• a digital-to-analog converter (DAC) outputting an analog voltage and comprising output voltage adjustment circuitry;
• a comparator receiving a reference voltage and the analog voltage;
• a control circuit operably connected to the comparator and the DAC in a feedback loop;
• and
• DAC step select logic,
• wherein the calibration circuit is selectively operable in a calibration mode and an operation mode,
• wherein, during the calibration mode, the output voltage adjustment circuitry increases a magnitude of the analog voltage by approximately a half DAC step and the control circuit uses the feedback loop to perform a binary search calibration process in order to identify a provisional DAC step, and
• wherein, during the operation mode, the output voltage adjustment circuitry decreases the magnitude of the analog voltage by approximately a half DAC step, the DAC step select logic selects one of the provisional DAC step and a next higher DAC step as a final DAC step, the control circuit outputs a final DAC code corresponding to the final DAC step, and the DAC generates a calibrated voltage in response to the final DAC code.

A calibration method comprising:

• operating a calibration circuit in a calibration mode, wherein the operating of the calibration circuit in the calibration mode comprises:
• adjusting a magnitude of an analog parameter output by a digital-to-analog converter (DAC) by approximately a half DAC step in a first direction;
• and
• using a feedback loop between a control circuit and the DAC to perform a binary search calibration process in order to identify a provisional DAC step;
• and
• operating the calibration circuit in an operation mode, wherein the operating of the calibration circuit in the operation mode comprises:
• adjusting the magnitude of the analog parameter output by the DAC by approximately a half DAC step in a second direction opposite the first direction;
• selecting either the provisional DAC step or an adjacent DAC step as a final DAC step;
• outputting a final DAC code corresponding to the final DAC step;
• and
• generating a calibrated parameter in response to the final DAC code.