Digital phase locked loop
AssigneeIndustry-University Cooperation Foundation Hanyang University
InventorChang Sik Yoo
Life of this patent
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Abstract
A digital phase locked loop realizing high bandwidth is disclosed. The digital locked loop generates a first digital code corresponding to a difference between a rising edge of a reference signal and a rising edge of a feedback signal and a second digital code corresponding to a difference between a falling edge of the reference signal and a falling edges of the feedback signal, generates a third digital code by adding the first digital code and the second digital code, generates a first frequency control code at the rising edge of the reference signal and a second frequency control code at the falling edge of the reference signal by filtering the third digital code, outputs a specific frequency depending on the first frequency control code and the second frequency control code.
Claims4
A digital phase locked loop comprising:
- a time-digital converter unit configured to output a first digital code corresponding to a rising edge phase difference signal including phase difference between rising edges of a reference signal and a feedback signal and a second digital code corresponding to a falling edge phase difference signal including phase difference between falling edges of the reference signal and the feedback signal;
- a digital adder configured to output a third digital code by adding the first digital code and the second digital code;
- a digital loop filter unit configured to output a first frequency control code at the rising edges of the reference signal and a second frequency control code at the falling edges of the reference signal by filtering the third digital code;
- and
- a digitally controlled oscillator configured to output a specific frequency depending on the first frequency control code and the second frequency control code,
- wherein the time-digital converter unit includes:
- a time-digital converter A configured to receive the reference signal and the feedback signal and output the first digital code by using the received reference signal and the received feedback signal;
- a NOT circuit A configured to perform a NOT operation about the reference signal;
- a NOT circuit B configured to perform a NOT operation about the feedback signal;
- and
- a time-digital converter B configured to receive an output value of the NOT circuit A and an output value of the NOT circuit B, and output the second digital code by using the received output values.
A digital phase locked loop comprising:
- a time-digital converter unit configured to output a first digital code corresponding to a rising edge phase difference signal including phase difference between rising edges of the reference signal and the feedback signal and a second digital code corresponding to a falling edge phase difference signal including phase difference between falling edges of the reference signal and the feedback signal;
- a digital adder configured to output a third digital code by adding the first digital code and the second digital code;
- a digital loop filter unit configured to output a frequency control code by low-pass-filtering the third digital code;
- and
- a digitally controlled oscillator configured to output a specific frequency depending on the frequency control code,
- wherein the time-digital converter unit includes:
- a time-digital converter A configured to receive the reference signal and the feedback signal and output the first digital code by using the received reference signal and the received feedback signal;
- a NOT circuit A configured to perform a NOT operation about the reference signal;
- a NOT circuit B configured to perform a NOT operation about the feedback signal;
- and
- a time-digital converter B configured to receive an output value of the NOT circuit A and an output value of the NOT circuit B, and output the second digital code by using the received output values.
Dependencies are inferred from the claim text.