VDS comparator rise P, fall P, on late, off late outputs for ZVC timing
AssigneeTexas Instruments Incorporated
InventorsJingwei Xu, Vijayalakshmi Devarajan, Gangqiang Zhang, Angelo William Pereira
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Abstract
Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.
Claims15
Comparator circuitry comprising:
- (a) a metal oxide semiconductor field effect transistor drain to source voltage, Vds, input;
- (b) a metal oxide semiconductor field effect transistor drain to source threshold voltage, VTH-ds, input;
- (c) a metal oxide semiconductor field effect transistor gate to source voltage, Vgs, clock input;
- (d) a metal oxide semiconductor field effect transistor gate to source threshold voltage, VTH-gs, input;
- and
- (e) an ON_LATE output;
- (f) an OFF_LATE output;
- and
- (g) Vds comparator circuitry having inputs coupled to the metal oxide semiconductor field effect transistor drain to source voltage, Vds, input and the metal oxide semiconductor field effect transistor drain to source threshold voltage, VTH-ds, input, and having a RISE P output and a FALL P output.
A process of operating a metal oxide semiconductor field effect transistor comprising:
- (a) comparing a metal oxide semiconductor field effect transistor drain to source voltage, Vds to a metal oxide semiconductor field effect transistor drain to source threshold voltage, VTH-ds;
- (c) latching an ON_LATE signal in response to the comparing and in response to a rising edge of a metal oxide semiconductor field effect transistor gate to source voltage, Vgs;
- (d) latching an OFF_LATE signal in response to the comparing and in response to a falling edge of the metal oxide semiconductor field effect transistor gate to source voltage, Vgs;
- and
- (e) timing the rising and falling edges of the gate to source Vgs voltage to the transistor in response to the ON_LATE signal and the OFF_LATE signal, the timing including timing the rising and falling edges of the gate to source Vgs voltage to provide a drain to source zero volt crossing timing.
Dependencies are inferred from the claim text.