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US 10,382,025 B2Granted
Circuit for meeting setup and hold times of a control signal with respect to a clock
AssigneeTexas Instruments Incorporated
InventorRobert Callaghan Taft
Life of this patent
Estimating the term…
Abstract
A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.
Claims13
A circuit, comprising:
- a plurality of series-coupled delay buffers;
- a plurality of logic gates, each logic gate including first and second inputs, the first input of each logic gate is coupled to a corresponding one of the delay buffers;
- and
- a plurality of flip-flops, each flip-flop including a data input and a data output, the data input coupled to an output of a corresponding one of the logic gates and the data output coupled to the second input of one of the corresponding logic gates;
- wherein each of the plurality of logic gates includes an exclusive-OR gate.
2 more elements
A circuit, comprising:
- a plurality of series-coupled delay buffers;
- a plurality of logic gates, each logic gate including first and second inputs, the first input of each logic gate is coupled to a corresponding one of the delay buffers;
- and
- a plurality of flip-flops, each flip-flop including a data input and a data output, the data input coupled to an output of a corresponding one of the logic gates and the data output coupled to the second input of one of the corresponding logic gates;
- wherein the plurality of logic gates is a first plurality of logic gates, and the circuit further includes a second plurality of logic gates, each of the second plurality of logic gates including third and fourth inputs, the third input of each of the second plurality of logic gates is coupled to the data input of a corresponding flip-flop and an output of a corresponding one of the first plurality of logic gates, and the fourth input is coupled to the data input of another one of the plurality of flip-flops.
2 more elements
A circuit, comprising:
- a plurality of series-coupled delay buffers;
- a plurality of logic gates, each logic gate including first and second inputs, the first input of each logic gate is coupled to a corresponding one of the delay buffers;
- a first plurality of flip-flops, each of the first plurality of flip-flops including a first data input and a first data output, the first data input coupled to an output of a corresponding one of the logic gates and the first data output coupled to the second input of one of the corresponding logic gates;
- and
- a second plurality of flip-flops, each of the second plurality of flip-flops including a second data input and a second data output, the second data input coupled to the first input of a corresponding one of the plurality of logic gates.
2 more elements
Dependencies are inferred from the claim text.