US 10,382,021 B2Granted

Flexible ripple mode device implementation for programmable logic devices

AssigneeLattice Semiconductor Corporation

InventorsBrad Sharpe-Geisler, Senani Gunaratna, Ting Yew

Life of this patent

Estimating the term…

Loading patent…

Abstract

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

Claims20

Dependent claims

A programmable logic device (PLD), comprising:

a plurality of programmable logic blocks (PLBs);
and
a plurality of logic cells within at least one of the PLBs, each logic cell comprising a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic, wherein:
each logic cell comprises a ripple register coupled to the associated carry logic and a generate register coupled to a generate circuitry of the logic cell;
each logic cell is configurable according to at least two selectable operational modes comprising a logic function output mode and a ripple arithmetic output mode, as determined by values of the ripple register and/or the generate register;
at least three of the 4-LUT inputs for each logic cell are interchangeable while a design is one or more of synthesized, mapped, placed, and/or routed into the plurality of logic cells when a selected operational mode for each logic cell comprises the ripple arithmetic output mode;
the 4-LUT comprises:
four two input lookup tables (2-LUTs) each configured to receive first and second input signals of the 4-LUT inputs;
and
two midlevel multiplexers each configured to receive a third input signal of the 4-LUT inputs and two 2-LUT output signals from the four 2-LUTs and provide a multiplexed signal, wherein the 4-LUT output signal is based at least on the two multiplexed signals;
and
the associated carry logic is configured to generate a carry output signal based on a carry input signal and the 4-LUT output signal.

9 more elements

A computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD);
and
synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:
detecting a ripple arithmetic operation in the design;
and
implementing the ripple arithmetic operation using at least one logic cell within a programmable logic block (PLB) of the PLD, each logic cell comprising a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic, wherein:
each logic cell comprises a ripple register coupled to the associated carry logic and/or a generate register coupled to a generate circuitry of the logic cell;
each logic cell is configurable according to at least two selectable operational modes comprising a logic function output mode and a ripple arithmetic output mode, as determined by values of the ripple register and/or the generate register;
at least three of the 4-LUT inputs for each logic cell are interchangeable while a design is one or more of synthesized, mapped, placed, and/or routed into the at least one logic cell when a selected operational mode for each logic cell comprises the ripple arithmetic output mode;
the 4-LUT of each logic cell comprises a level restoring stage configured to provide a tap signal to the generate circuitry of the logic cell;
the level restoring stage comprises an inverter configured to provide the tap signal;
the 4-LUT further comprises a decode block configured to receive first and second input signals of the 4-LUT inputs and four two input lookup tables (2-LUTs);
and
the decode block is configured to provide a quaternary decode signal to the four 2-LUTs.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/658,349Filed 24 Jul 2017 · continuation
Priority: 24 Jul 2014
Published: US 2017/0324400 A19 Nov 2017
Granted: 13 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03K 3/35625
Of the primary-secondary type: using complementary field-effect transistors
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing

Family

Application62/028,441Us provisional application · filed 24 Jul 2014
Application14/610,074Parent of this continuation · filed 30 Jan 2015
US 2017/0324400 A1Pre-grant publication · published 9 Nov 2017
US 9,735,761 B2Parent of this continuation
US 2016/0028400 A1Published application
US 10,382,021 B2This patent

From the US filing history. Foreign family members aren’t listed.