Ultra-low power static state flip flop

A flip-flop, comprising:

• a tri-state inverter;
• a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate, the master latch receives a clock signal;
• a slave latch coupled to the master latch and comprising a second transistor and a second inverter, the slave latch receives the clock signal;
• and
• an enablement logic coupled to the master latch and comprising multiple, additional logic gates,
• wherein the tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static;
• wherein the first transistor is an NMOS switch, and wherein the master latch further comprises a second NMOS switch coupled to the NMOS switch and a PMOS switch coupled to the second NMOS switch, and wherein the first logic gate is a NAND logic gate coupled to the tri-state inverter and the enablement logic;
• wherein the first inverter couples to a gate of the NMOS switch, and wherein an output of the tri-state inverter couples to an input of the first inverter and to an input of the first logic gate.