Dynamic flip flop having data independent P-stack feedback

A dynamic flip flop, comprising:

• a P-stack feedback circuit, including:
• a first P-type transistor gated by a first dynamic inverted signal;
• and
• a second P-type transistor gated by an inverted clock signal, wherein:
• a drain of the second P-type transistor is coupled to a source of the first P-type transistor;
• a source of the second P-type transistor is coupled to a node that is configured to receive a second dynamic inverted signal;
• and
• an N-stack section including an N-type transistor gated by a data input signal,
• wherein the N-type transistor is referred to as a first N-type transistor, and wherein the N-stack section further includes:
• a second N-type transistor gated by a feedback signal;
• a third N-type transistor gated by a clock signal;
• and
• a fourth N-type transistor gated by the first dynamic inverted signal.

A circuit of a dynamic flip flop, the circuit comprising:

• a P-stack feedback circuit, including:
• a first P-type transistor gated by a first dynamic inverted signal;
• and
• a second P-type transistor gated by an inverted clock signal, wherein:
• a drain of the second P-type transistor is coupled to a source of the first P-type transistor;
• and
• a source of the second P-type transistor is coupled to a node that is configured to receive a second dynamic inverted signal;
• and
• an N-stack section including a plurality of N-type transistors each gated by a data input signal.