Adaptive oscillator for clock generation

A system comprising:

• a plurality of components in an integrated circuit, the integrated circuit including a clock tree;
• a frequency locked loop circuit that generates a system clock that drives the clock tree;
• and
• an oscillator circuit within the frequency locked loop circuit comprising:
• a first delay line coupled to a first voltage that outputs a first delayed signal, wherein the first voltage is a regulated supply voltage;
• a second delay line coupled to a second voltage that outputs a second delayed signal, wherein the second voltage is a droopy supply voltage;
• and
• an edge detector generating an output clock based on a relationship between the first delayed signal and the second delayed signal, the output clock having a first feedback path to an input of the first delay line and a second feedback path to an input of the second delay line.