Resistive memory crossbar array compatible with Cu metallization
AssigneeInternational Business Machines Corporation
InventorsTakashi Ando, Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen
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Abstract
A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.
Claims20
A method for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array, the method comprising:
- forming a plurality of conductive lines within an interlayer dielectric (ILD);
- forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask;
- forming a low-k dielectric layer over the RRAM stack;
- removing a first layer of the bi-layer hardmask during a via opening;
- and
- removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.
A method for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array, the method comprising:
- forming a plurality of conductive lines within an interlayer dielectric (ILD);
- forming a metal nitride layer in direct contact with a conductive line of the plurality of conductive lines;
- forming a RRAM including at least a dual layer hardmask;
- removing a first layer of dual layer hardmask during a via opening;
- and
- removing a second layer of the dual layer hardmask concurrently with a plurality of sacrificial layers formed over a low-k dielectric layer deposited in direct contact with the RRAM stack.
A semiconductor structure for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array, the semiconductor structure comprising:
- a plurality of conductive lines disposed within an inter-layer dielectric (ILD);
- a barrier layer disposed in direct contact with a conductive line of the plurality of conductive lines;
- a bottom electrode disposed over the barrier layer;
- a high-k dielectric layer disposed over the bottom electrode;
- a top electrode disposed over the high-k dielectric layer;
- outer spacers disposed adjacent the bottom electrode, the high-k dielectric layer, and the top electrode, the outer spacers extending vertically beyond a top surface of the top electrode to create a step-like via landing;
- and
- a conductive material disposed over the top electrode.
Dependencies are inferred from the claim text.