Resistive memory device having a retention layer
Assignee4D-S, Ltd.
InventorsSeshubabu Desu, Michael Van Buskirk
Life of this patent
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Abstract
A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 1×10-4 ohm-m.
Claims20
A memory device, comprising:
- a bottom contact;
- a memory layer connected to the bottom contact, wherein the memory layer has a variable resistance;
- a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure;
- and
- a retention layer between the memory layer and the top electrode, wherein the retention layer has a variable ionic conductivity, wherein the retention layer is configured to selectively resist ionic conduction, and wherein the resistivity of the retention layer is less than 1×10−4 Ohm-m.
A method of manufacturing a memory device, comprising:
- forming a bottom contact;
- connecting a memory layer to the bottom contact, wherein the memory layer has a variable resistance;
- forming a conductive top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure;
- and
- forming a retention layer between the memory layer and the top electrode, wherein the retention layer has a variable ionic conductivity, wherein the retention layer is configured to selectively resist ionic conduction, and wherein the resistivity of the retention layer is less than 1×10−4 Ohm-m.
A method of using a memory device, the memory device comprising a bottom contact, a memory layer with a variable resistance connected to the bottom contact, a conductive top electrode on the memory layer, and a retention layer between the memory layer and the top electrode, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, wherein the retention layer has a variable ionic conductivity, wherein the retention layer is configured to selectively resist ionic conduction, and wherein the resistivity of the retention layer is less than 1×10−4 Ohm-m, the method comprising:
- applying a first voltage difference across the bottom contact and the top electrode, whereby an electric field is generated in the memory layer, and such that a resistivity state of the memory layer is changed;
- applying a second voltage difference across the bottom contact and the top electrode;
- while the second voltage difference is applied, causing a first current to be conducted through the bottom contact, the memory layer, the retention layer, and the top electrode;
- and
- determining the resistivity state of the memory layer based on the second voltage and the first current.
Dependencies are inferred from the claim text.