Semiconductor devices

A semiconductor device, comprising:

• a first transistor having a positive first threshold voltage, the first transistor including:
• first channels on a first region of a substrate including the first region and a second region, the first channels being spaced apart from each other in a vertical direction on an upper surface of the substrate;
• first source/drain layers on the first region of the substrate, the first source/drain layers being connected to respective opposite sidewalls of the first channels;
• and
• a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked from a surface of each of the first channels;
• a second transistor having a positive second threshold voltage greater than the positive first threshold voltage, the second transistor including:
• second channels on the first region of the substrate, the second channels being spaced apart from each other in the vertical direction on the upper surface of the substrate;
• second source/drain layers on the first region of the substrate, the second source/drain layers being connected to respective opposite sidewalls of the second channels;
• and
• a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked from a surface of each of the second channels;
• and
• a third transistor having a negative third threshold voltage, the third transistor including:
• third channels on the second region of the substrate, the third channels being spaced apart from each other in the vertical direction on the upper surface of the substrate;
• third source/drain layers on the substrate, the third source/drain layers being connected to respective opposite sidewalls of the third channels;
• and
• a third gate structure surrounding the third channels and including a third gate insulation pattern and a third threshold voltage control pattern sequentially stacked from a surface of each of the third channels,
• wherein the first threshold voltage control pattern has a first pattern having a first material composition, the second threshold voltage control pattern has a second pattern having a second material composition different from the first material composition, and the third threshold voltage control pattern has the first and second patterns.