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US 10,381,482 B2Granted
Passivated and faceted for fin field effect transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
Life of this patent
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Abstract
A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
Claims20
A fin field effect transistor (FinFET) comprising:
- a substrate;
- a fin structure protruding from the substrate, the fin structure comprising one or more semiconductor layers, each of the one or more semiconductor layers having a different lattice constant than an immediately underlying layer;
- an isolation region adjacent opposing sidewalls of the fin structure, the fin structure having a channel region above the isolation region and a lower portion below the isolation region and the channel region, the channel region adjoining the lower portion at a first point, wherein sidewalls of the channel region extending away from the first point have a first slope and sidewalls of the lower portion extending away from the first point have a second slope, the first slope being different than the second slope, a total width of the fin structure decreases as the fin structure extends away from the first point;
- and
- a gate structure overlying the channel region of the fin structure along a direction orthogonal to a major surface of the substrate.
2 more elements
A fin field effect transistor (FinFET) comprising:
- a substrate having a fin structure, a first section of the fin structure comprising one or more semiconductor layers, each of the one or more semiconductor layers having a different lattice constant than an immediately underlying layer, the first section of the fin structure having a first sidewall, the first sidewall having an upper sidewall and a lower sidewall, the upper sidewall having a first slope, the lower sidewall having a second slope, the first slope being different than the second slope, the upper sidewall being a sidewall of a channel region;
- an isolation region adjacent first opposing sidewalls of the fin structure, an upper surface of the isolation region having a first point closest to the first sidewall, the first point being level with a junction between the upper sidewall and the lower sidewall;
- a first passivation layer interposed between the fin structure and the isolation region;
- and
- a gate structure overlying the upper sidewall having the first slope, the gate structure extending along second opposing sidewalls of the first section of the fin structure, wherein a total width of the fin structure directly below the gate structure narrows as the fin structure extends away from the isolation region.
2 more elements
A fin field effect transistor (FinFET) comprising:
- a fin structure comprising one or more semiconductor layers, each semiconductor layer of the one or more semiconductor layers having a different lattice constant of an immediately underlying semiconductor layer of the one or more semiconductor layers, the fin structure having a first sidewall;
- an isolation region on opposing sides of the fin structure, the fin structure extending above the isolation region;
- a gate dielectric layer over a first section of the fin structure, the first section of the fin structure being interposed between a source region and a drain region, the gate dielectric layer and the isolation region having a first interface, wherein a lower sidewall of the first section of the fin structure extending away from the first interface has a first slope, an upper sidewall of the first section of the fin structure extending away from the first interface has a second slope different than the first slope, the lower sidewall being below the first interface, the upper sidewall being above the first interface, wherein the fin structure below the first interface comprises a first semiconductor composition and the fin structure above the first interface comprises a second semiconductor composition different than the first semiconductor composition, wherein a second interface between the first semiconductor composition and the second semiconductor composition is level with the first interface between the gate dielectric layer and the isolation region;
- and
- a gate electrode over the gate dielectric layer.
2 more elements
Dependencies are inferred from the claim text.