US 10,381,479 B2 · Interface charge reduction for SiGe surface

Abstract

Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

Claims20

Dependent claims

A method for reducing interface charge density (Dit) for a silicon germanium (SiGe) channel material, the method comprising the steps of:

contacting the SiGe channel material with an n-dopant precursor under conditions sufficient to chemically dope a surface of the SiGe channel material with an n-type dopant;
contacting the SiGe channel material with a silicon (Si)-containing chemical precursor under conditions sufficient to form a thin continuous Si layer on a surface of the SiGe channel material, wherein the SiGe channel material is contacted with the n-dopant precursor prior to contacting the SiGe channel material with the Si-containing chemical precursor;
and
depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit.

1 more element

A method of forming a field effect transistor (FET) device, the method comprising the steps of:

epitaxially growing a SiGe channel material on a substrate;
contacting the SiGe channel material with an n-dopant precursor under conditions sufficient to chemically dope a surface of the SiGe channel material with an n-type dopant;
contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer on a surface of the SiGe channel material, wherein the SiGe channel material is contacted with the n-dopant precursor prior to contacting the SiGe channel material with the Si-containing chemical precursor;
forming a gate stack on the SiGe channel material, wherein the gate stack comprises a gate dielectric on the SiGe channel material over the thin continuous Si layer and a gate conductor on the gate dielectric, and wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric.

1 more element

Dependencies are inferred from the claim text.

Interface charge reduction for SiGe surface

Life of this patent

Interface charge reduction for SiGe surface

Life of this patent

Abstract

Claims20