Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device
AssigneesSTMicroelectronics (Crolles 2) SAS, Commissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsFrederic Boeuf, Olivier Weber
Life of this patent
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Abstract
A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
Claims7
A device, comprising:
- a substrate of the silicon on insulator type comprising a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate,
- wherein the semi-conducting film comprises at least one first film zone comprising tensile-stressed silicon and at least one second film zone comprising tensile-relaxed silicon,
- an NMOS transistor formed on and in the tensile-stressed silicon of the first film zone;
- and
- a PMOS transistor formed on and in the tensile-relaxed silicon of the second film zone;
- wherein the buried insulating layer comprises at least one opening under the at least one second film zone, the opening filled with unstressed silicon extending from said unstressed silicon support substrate to the tensile-relaxed silicon of the at least one second film zone to provide a contact well for contacting the unstressed silicon support substrate.
A device, comprising:
- an unstressed silicon support substrate;
- a buried insulating layer on the unstressed silicon support substrate;
- a first film of tensile-stressed silicon on the buried insulating layer in a first zone;
- an NMOS transistor disposed in and on the first film of tensile-stressed silicon;
- a second film of tensile-relaxed silicon on the buried insulating layer in a second zone;
- a PMOS transistor disposed in and on the second film of tensile-relaxed silicon;
- a first shallow trench isolation surrounding the first film of tensile-stressed silicon;
- a second shallow trench isolation surrounding the second film of tensile-relaxed silicon;
- and
- wherein a portion of the unstressed silicon support substrate extends between the first shallow trench isolation second shallow trench isolation to provide a contact well extending from the second film of tensile-relaxed silicon to the unstressed silicon support substrate.
Dependencies are inferred from the claim text.