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US 10,381,468 B2Granted
Method and structure for forming improved single electron transistor with gap tunnel barriers
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.
Claims16
A method for manufacturing a semiconductor device, comprising:
- forming a stacked configuration of semiconductor layers on a substrate comprising a first semiconductor layer on the substrate, wherein the stacked configuration comprises:
- a first sacrificial semiconductor layer on the first semiconductor layer;
- a second semiconductor layer on the first sacrificial semiconductor layer;
- a second sacrificial semiconductor layer on the second semiconductor layer;
- and
- a third semiconductor layer on the second sacrificial semiconductor layer;
- performing a first patterning of the stacked configuration and the first semiconductor layer by removing first portions of the stacked configuration and the first semiconductor layer;
- forming gate structures in place of the removed first portions of the stacked configuration and the first semiconductor layer;
- performing a second patterning of the stacked configuration and the first semiconductor layer by removing second portions of the stacked configuration and the first semiconductor layer;
- selectively removing from the stacked configuration the first and second sacrificial semiconductor layers exposed by the second patterning to create a first gap and a second gap respectively in place of the selectively removed first and second sacrificial semiconductor layers;
- and
- forming a dielectric layer in place of the removed second portions of the stacked configuration and the first semiconductor layer;
- wherein the first and second gaps are tunnel barriers of a single electron transistor (SET) of the semiconductor device.
10 more elements
A method for manufacturing a semiconductor device, comprising:
- forming a stacked configuration of semiconductor layers on a substrate comprising a first semiconductor layer on the substrate, wherein the stacked configuration comprises:
- a first sacrificial layer on the first semiconductor layer;
- a second semiconductor layer on the first sacrificial layer;
- a second sacrificial layer on the second semiconductor layer;
- and
- a third semiconductor layer on the second sacrificial layer;
- wherein the first and third semiconductor layers are doped;
- performing a first patterning of the stacked configuration and the first semiconductor layer by removing first portions of the stacked configuration and the first semiconductor layer;
- forming gate structures in place of the removed first portions of the stacked configuration and the first semiconductor layer;
- performing a second patterning of the stacked configuration and the first semiconductor layer by removing second portions of the stacked configuration and the first semiconductor layer;
- selectively removing from the stacked configuration the first and second sacrificial layers exposed by the second patterning to create a first gap and a second gap respectively in place of the selectively removed first and second sacrificial layers;
- and
- forming a dielectric layer in place of the removed second portions of the stacked configuration and the first semiconductor layer;
- wherein the first and second gaps are tunnel barriers of a single electron transistor (SET) of the semiconductor device.
11 more elements
Dependencies are inferred from the claim text.