Nanowire FET including nanowire channel spacers
AssigneeInternational Business Machines Corporation
InventorSoon-Cheon Seo
Life of this patent
Estimating the term…
Abstract
A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.
Claims19
A stacked nanowire field effect transistor (FET) comprising:
- a plurality of vertically stacked nanowire channels, each nanowire channel vertically separated from one another by sacrificial segment;
- a gate stack on the upper surface of the semiconductor substrate, the gate stack including a conductive element that wraps around the nanowire channels;
- source/drain regions on the upper surface of the semiconductor substrate, the source/drain regions directly contacting ends of the nanowire channel;
- and
- nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack,
- wherein the ends include a first end that extends beneath the gate stack and an opposing second end that contacts inner sidewalls of the source/drain regions.
A method of forming nanowire channel spacers in a nanowire field effect transistor (FET), the method comprising:
- forming a multi-stack semiconductor fin on an upper surface of a semiconductor substrate, the multi-stack semiconductor fin comprising a plurality of vertically stacked semiconductor material layers including plurality of nanowire channel layers, each nanowire channel layer vertically separated from one another by a sacrificial layer;
- forming source/drain regions on the upper surface of the semiconductor substrate, the source/drain regions contacting the multi-stack fin;
- and
- forming a void that exposes portions of the sacrificial layers and the nanowire channel layers;
- etching the exposed portions of the sacrificial layers to form cavities that release opposing ends of the nanowire channel layers and form stacked nanowire channels;
- and
- filing the cavities with a spacer material that encapsulates the released ends and forms the nanowire channel spacers.
A stacked nanowire field effect transistor (FET) comprising:
- a plurality of vertically stacked nanowire channels, each nanowire channel vertically separated from one another by sacrificial segment;
- a gate stack on the upper surface of the semiconductor substrate, the gate stack including a conductive element that wraps around the nanowire channels;
- source/drain regions on the upper surface of the semiconductor substrate, the source/drain regions directly contacting ends of the nanowire channel;
- and
- nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack,
- wherein the nanowire channel spacers are interposed between the source/drain regions and ends of the sacrificial segment.
Dependencies are inferred from the claim text.