Semiconductor device and method for manufacturing the same
AssigneeMagnaChip Semiconductor, Ltd.
InventorsYu Shin Ryu, Bo Seok Oh, Jin Yeong Son
Life of this patent
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Abstract
A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.
Claims24
A method for manufacturing a semiconductor device comprising:
- forming an isolation region in a substrate;
- forming an extended drain junction region in a well region of the substrate;
- forming two or more gate insulating layers comprising a thinner portion and a thicker portion on the extended drain junction region in the well region;
- and
- forming a gate electrode on an entire top surface of each of the gate insulating layers,
- wherein the extended drain junction region overlapping with the thicker portion of the two or more gate insulating layers has a depth shallower than a depth of the isolation region with respect to a top surface of the substrate.
A method for manufacturing a semiconductor device comprising:
- forming an isolation region in a substrate;
- forming a well region having a depth deeper than a depth of the isolation region in the substrate;
- forming a medium well region and an extended drain junction region in the well region;
- forming two or more gate insulating layers having different thicknesses on the extended drain junction region in the well region;
- forming a gate electrode on the gate insulating layers;
- and
- forming a source region and a drain region on both sides of the gate electrode,
- wherein the extended drain junction region contacts the two or more gate insulating layers having different thicknesses, and
- wherein the medium well region is disposed between the extended drain junction region and the drain region, and the medium well region has a depth deeper than a depth of the extended drain junction region.
A method for manufacturing a semiconductor device comprising:
- forming an isolation region in a substrate;
- forming a high voltage well region in the substrate;
- forming a well region in the high voltage well region, the well region having a same conductivity type as that of the high voltage well region;
- forming an extended drain junction region in direct contact with the well region in the high voltage well region;
- forming a thick gate insulation layer in direct contact with the extended drain junction region;
- forming a thin gate insulation layer in direct contact with the extended drain junction region and the well region;
- forming a gate electrode on both an entire top surface of the thick gate insulation layer and an entire top surface of the thin gate insulation layer;
- and
- forming a source region and a drain region on both sides of the gate electrode,
- wherein the extended drain junction region overlaps with the gate electrode.
A method for manufacturing a semiconductor device, the method comprising:
- forming an isolation region in a substrate;
- forming an extended drain junction region in the substrate;
- forming a triple gate oxide layer on the extended drain region, the triple gate oxide layer comprising a first gate insulating layer, a second gate insulating layer and a third gate insulating layer, and the third gate insulating layer having a thickness greater than a thickness of the second gate insulating layer which is greater than a thickness of the first gate insulating layer;
- forming a gate electrode on the triple gate oxide layer;
- and
- forming a source region and a drain region on both sides of the gate electrode,
- wherein the extended drain junction region contacts the second gate insulating layer, and
- wherein the extended drain junction region overlapping with the second gate insulating layer has a depth shallower than a depth of the isolation region from a top surface of the substrate.
Dependencies are inferred from the claim text.