Transistor with contacted deep well region

A transistor comprising:

• an insulating layer located on a planar surface of an active layer;
• a gate electrode located on the insulating layer, wherein a plan view overlap of the gate electrode and the insulating layer encompasses a channel region in a body region in the active layer;
• a source region in contact with the body region and located on the planar surface of the active layer, wherein the body region and the source region have opposite conductivity types;
• a deep well region in contact with the source region and the body region, wherein the deep well region and the source region have opposite conductivity types;
• a source contact that is in physical contact with the deep well region and the source region;
• wherein the source contact is in physical contact with the deep well region at the planar surface of the active layer and
• a gate shield region separated from the gate electrode by a first dielectric region;
• wherein:
• the source contact provides an ohmic contact to the gate shield region;
• in a cross section view of the transistor, a first region of the gate shield region extends over an entirety of the gate electrode, a bottom surface of the first region of the gate shield region being above a top surface of the gate electrode;
• and
• in the cross section view of the transistor, a second region of the gate shield region extends over a portion of the planar surface of the active layer, a bottom surface of the second region of the gate shield region being below and offset from a bottom surface of the gate electrode and being separated from the planar surface of the active layer by a second dielectric region.