Back to results
US 10,381,452 B2Granted
Asymmetric high-k dielectric for reducing gate induced drain leakage
AssigneeInternational Business Machines Corporation
InventorsAnthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
Life of this patent
Estimating the term…
Abstract
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Claims11
A gate structure comprising:
- a dielectric layer on substrate, a source side and a drain side of the gate structure, the dielectric layer having a first thickness on the source side and a second thickness on the drain side to form a asymmetric gate dielectric;
- sidewalls on gate material on the source side and the drain side;
- and
- a high-k dielectric layer on the sidewalls on the drain side and underlying the gate material,
- wherein the dielectric layer is an oxide layer on the drain side of the gate structure.
2 more elements
Dependencies are inferred from the claim text.