Three-dimensional memory device with self-aligned drain select level isolation structures and method of making thereof

A three-dimensional memory device, comprising:

• an alternating stack of insulating layers and electrically conductive layers located over a substrate;
• an insulating fill material layer and drain select gate electrodes located over the alternating stack;
• and
• a group of memory stack structures extending through the alternating stack and arranged as rows of memory stack structures, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film,
• wherein each drain select gate electrode is laterally surrounded by the insulating fill material layer;
• and
• wherein the insulating fill material layer comprises:
• a drain select level isolation structure located between neighboring rows of memory stack structures within the group of memory stack structures, extending along a first horizontal direction, and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions that contact convex vertical sidewalls of the memory stack structures;
• and
• a drain select level field dielectric portion adjoined to the drain select level isolation portion and contacting sidewalls of the drain select gate electrodes that extend along a second horizontal direction that is perpendicular to the first horizontal direction;
• wherein:
• the insulating fill material layer has a homogeneous dielectric composition throughout;
• the group of memory stack structures is arranged as multiple rows of memory stack structures such that the rows are spaced apart along the second horizontal direction with a uniform inter-row pitch for an entirety of the group of memory stack structures;
• each of the select gate electrodes comprises a semiconductor material select gate electrode portion containing a doped semiconductor matrix and a doped semiconductor liner;
• and
• the doped semiconductor matrix and the doped semiconductor liner have a doping of a same conductivity type.