Field effect transistor and method of making

A method comprising:

• forming, at a semiconductor substrate, a gate electrode over a channel region of a Field Effect Transistor (FET);
• forming a comb-shaped drain electrode electrically connected to a drain diffusion region, the comb-shaped drain electrode having multiple comb-shaped drain electrode layers at corresponding multiple levels overlying the semiconductor substrate, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same drain electrode finger width dimension, a number of vias between each two corresponding drain electrode fingers at adjacent levels is substantially the same;
• and
• forming a comb-shaped source electrode electrically connected to a source diffusion region, the comb-shaped source electrode having multiple comb-shaped source electrode layers at the corresponding multiple levels, each comb-shaped source electrode layer including a plurality of source electrode fingers having substantially the same source electrode finger width dimension, wherein a number of vias between each two corresponding source electrode fingers at adjacent levels is substantially the same, and wherein an amount of intra-level interleaving of the drain electrode fingers and the source electrode fingers is different at each one of the corresponding levels.

A device comprising:

• a Field Effect Transistor (FET) having a gate electrode overlying a channel region,
• a comb-shaped drain electrode electrically connected to a drain diffusion region of the FET, and having multiple comb-shaped drain electrode layers at corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers;
• a comb-shaped source electrode electrically connected to a source diffusion region of the FET, and having multiple comb-shaped source electrode layers at the corresponding levels, each comb-shaped source electrode layer including a plurality of source electrode fingers interleaved with the plurality of drain electrode fingers;
• a number of vias between each two corresponding drain electrode fingers at adjacent levels is substantially the same;
• and
• a number of vias between each two corresponding source electrode fingers at adjacent levels is substantially the same.