Memory cell and non-volatile semiconductor storage device

A memory cell comprising:

• a memory well;
• a drain region disposed on a memory well surface of the memory well and connected to a bit line;
• a source region disposed on the memory well surface and connected to a source line;
• a memory gate structure disposed between the drain region and the source region and including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked in this order over the memory well, the memory gate structure having a first sidewall and a second sidewall;
• a first select gate structure disposed between the drain region and the memory gate structure and including a first select gate insulating film disposed on the memory well and including a first select gate electrode disposed on the first select gate insulating film;
• a second select gate structure disposed between the source region and the memory gate structure and including a second select gate insulating film disposed on the memory well and including a second select gate electrode disposed on the second select gate insulating film;
• a first sidewall spacer disposed between the memory gate structure and the first select gate structure and including a first insulating layer and a first sidewall layer disposed in the first insulating layer, the first sidewall layer being made of an insulating material different from an insulating material of the first insulating layer, the first sidewall layer being disposed along the first sidewall of the memory gate structure and at a predetermined distance from the first sidewall of the memory gate structure such that the first sidewall layer is apart from the charge storage layer;
• and
• a second sidewall spacer disposed between the memory gate structure and the second select gate structure and including a second insulating layer and a second sidewall layer disposed in the second insulating layer, the second sidewall layer being made of an insulating material different from an insulating material of the second insulating layer, the second sidewall layer being disposed along the second sidewall of the memory gate structure and at the predetermined distance from the second sidewall of the memory gate structure such that the second sidewall layer is apart from the charge storage layer,
• wherein a distance between the memory well surface and a lower surface of each of the first and second sidewall layers is greater than a thickness of the lower memory gate insulating film,
• the first sidewall layer is disposed in the first sidewall spacer to separate the memory gate electrode from the first select gate electrode,
• the second sidewall layer is disposed in the second sidewall spacer to separate the memory gate electrode from the second select gate electrode,
• a width of each of the first and second sidewall spacers is greater than or equal to 5 nm, and
• a thickness of each of the first and second select gate insulating films is less than or equal to 3 nm.