Low resistance source drain contact formation

A device, comprising:

• a p-type transistor comprising source and drain regions interconnected by a channel region, and at least one gate configured to regulate current flow through the channel region;
• a dielectric over the p-type transistor;
• contact trenches present in the dielectric over, and extending down to, the source and drain regions;
• an epitaxial material within the contact trenches;
• and
• a crystalline gallium-doped layer on the epitaxial material having a homogenous gallium (Ga) concentration of from about 6×1020 at./cm3 to about 8×1021 at./cm3, and ranges therebetween, whereby a layered contact structure is provided comprising three distinct regions including:
• i) a first region comprising the crystalline gallium-doped layer, ii) a second region, beneath the crystalline gallium-doped layer, comprising the epitaxial material, and iii) a third region, beneath the epitaxial material, comprising the source and drain regions, wherein the first region, the second region and third region each comprises a germanium-containing semiconductor with the first region and the second region having a higher percentage of germanium than the third region, and wherein the first region has the homogenous gallium concentration of from about 6×1020 at./cm3 to about 8×1021 at./cm3, and ranges therebetween, and wherein the first region comprising the crystalline gallium-doped layer is directly in contact with the third region comprising the source and drain regions.