Nanowire transistor having two spacers between gate structure and source/drain structure

A nanowire transistor, comprising:

• a substrate having a first region and a second region;
• a first nanowire channel layer on the first region and a second nanowire channel layer on the second region;
• a first gate structure on the first nanowire channel layer and a second gate structure on the second nanowire channel layer;
• a first source/drain structure adjacent to two sides of the first gate structure and contacting the substrate directly, wherein the first source/drain structure comprises metal and a top surface of the first source/drain structure is lower than a top surface of the first gate structure;
• a second source/drain structure adjacent to two sides of the second gate structure and contacting the substrate directly, wherein the second source/drain structure comprises semiconductor material;
• a first spacer between and directly contacting the first nanowire channel layer and the first source/drain structure;
• a second spacer between and directly contacting the second nanowire channel layer and the second source/drain structure;
• and
• a third spacer on a lateral sidewall of the first gate structure and a fourth spacer on a lateral sidewall of the second gate structure.