US 10,381,436 B2Granted

Semiconductor device and method of manufacturing semiconductor device

AssigneeFuji Electric Co., Ltd.

InventorsIsamu Sugai, Takeyoshi Nishimura

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Abstract

To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 μm or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Claims5

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming, at an upper surface side of a semiconductor substrate, a first conductivity-type drift region, a second conductivity-type base region, a first conductivity-type source region, and two or more gate trenches penetrating through the source region and the base region;
forming a contact trench between two gate trenches, penetrating through the source region, and including a lower end of the contact trench arranged in the base region;
and
implanting impurities below the base region from the lower end of the contact trench to form a second conductivity-type protruding portion protruding toward a lower side from a lower end of the base region in a region opposite to the lower end of the contact trench, wherein
a carrier concentration Nd of a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a following equation
0.9
≦
Wc
-
Wt
Wt
×
Nd
Na
≦
1.1
[
Equation
⁢
⁢
1
]
wherein Wc is an interval between the two gate trenches, and Wt is a width of the contact trench.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/983,060Filed 17 May 2018 · continuation
Priority: JP 2016-09791116 May 2016
Published: US 2018/0269281 A120 Sep 2018
Granted: 13 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
H10D 30/0295
Of vertical dmos [vdmos] fets: using recessing of the source electrodes
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors

Family

Application15/473,636Parent of this continuation · filed 30 Mar 2017
US 2018/0269281 A1Pre-grant publication · published 20 Sep 2018
US 10,026,807 B2Parent of this continuation
US 2017/0330932 A1Published application
US 10,381,436 B2This patent

From the US filing history. Foreign family members aren’t listed.