Method to fabricate discrete vertical transistors
AssigneeWestern Digital Technologies, Inc.
InventorsMac D. Apodaca, Daniel Robert Shepard
Life of this patent
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Abstract
The present disclosure generally relates to the fabrication of metal-oxide-semiconductor (MOS) select transistors in a vertical orientation such that the transistor pair fits within the footprint of a 4F2 memory cell. The present disclosure further relates to the simultaneous fabrication of a vertical stack of transistors in which each transistor is distinct, as opposed to being serially connected in a NAND-like string. An initial stack of materials is built to include silicon layers to act as source and drain regions as well as to serve as epitaxial growth seed points. As such, the transistor disclosed may be utilized in conjunction with memory elements such as Phase Change, Resistive, or Magnetic RAM memory within array designs, among others.
Claims19
A memory cell, comprising:
- a first plurality of layers deposited on a substrate;
- a first hardmask deposited on the first plurality of layers, wherein a first plurality of trenches are formed through the first hardmask and the first plurality of layers;
- an epitaxial silicon material comprising a rounded shape and disposed on a sidewall of each of the first plurality of trenches;
- an oxide material deposited in each of the first plurality of trenches;
- a gate oxide layer deposited in each of the first plurality of trenches;
- a first metal material deposited over the gate oxide layer within each of the first plurality of trenches;
- a second plurality of trenches formed parallel to the first plurality of trenches and through the first hardmask and the first plurality of layers, wherein the second plurality of trenches are at least partially filled with a dielectric material, and wherein at least one of the second plurality of trenches comprises a second metal material such that a first width of the dielectric material below the second metal material is wider than a second width of the dielectric material above the second metal material.
A vertical memory cell, comprising:
- a first layer;
- a second layer;
- and
- a plurality of transistors, comprising:
- a first transistor disposed within the first layer and having a source node coupled to a first voltage source and a drain node coupled to a word line of the vertical memory cell,
- a second transistor disposed within the first layer and having a source node coupled to a second voltage source and a drain node coupled to a bit line of the vertical memory cell,
- a third transistor disposed within the second layer and having a source node coupled to the drain node of the first transistor, and
- a fourth transistor disposed within the second layer and having a source node coupled to the drain node of the second transistor,
- wherein gate electrodes of the first and second transistors are coupled to a same node.
A memory device, comprising:
- a memory cell disposed at an intersection between a bit line and a word line;
- a first transistor disposed within a first layer and comprising:
- a first source node coupled to a first source voltage potential,
- a first drain node coupled to the word line, and
- a first gate node coupled to a common node;
- a second transistor disposed within the first layer and comprising:
- a second source node coupled to a second source voltage potential,
- a second drain node coupled to the bit line, and
- a second gate node coupled to the common node;
- a third transistor disposed within a second layer and comprising:
- a third source node coupled to the drain node of the first transistor,
- a third drain node coupled to ground, and
- a third gate node coupled to a first control line;
- and
- a fourth transistor disposed within the second layer and comprising:
- a fourth source node coupled to the drain node of the first transistor,
- a fourth drain node coupled to ground, and
- a fourth gate node coupled to a second control line.
Dependencies are inferred from the claim text.