Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for dual bit operation and methods for fabricating the same

A method for fabricating an integrated circuit comprising a plurality of magnetic random access memory (MRAM) structures, the method comprising:

• forming a first lower magnetic tunnel junction stack (MTJ stack) overlying a semiconductor substrate with the first lower MTJ stack comprising a first lower free layer;
• forming a spin orbit torque coupling layer overlying the first lower MTJ stack;
• forming a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack;
• forming a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack with the first upper MTJ stack comprising a first upper free layer;
• forming a second lower MTJ stack spaced from said first lower MTJ stack and overlying said semiconductor substrate;
• forming a dielectric layer disposed between said first lower MTJ stack and said second lower MTJ stack, said dielectric layer overlying said semiconductor substrate, and said spin orbit torque coupling layer overlying said first lower MTJ stack, said dielectric layer, and said second lower MTJ stack;
• and
• forming a second upper MTJ stack overlying said spin orbit torque coupling layer and said second lower MTJ stack.