Three-dimensional vertical NOR flash thin-film transistor strings

A memory structure, comprising:

• a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operation;
• a plurality of active columns of semiconducting material formed above the semiconductor substrate, each active column extending along a first direction orthogonal to the planar surface of semiconductor substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped regions, wherein the active columns are arranged in a two-dimensional array having rows of active columns extending along a second direction and rows of active columns extending along a third direction, the second direction and the third direction each being parallel to the planar surface of the semiconductor substrate;
• charge-trapping material provided over one or more surfaces of each active columns;
• and
• a plurality of word line conductors that are electrically isolated from each other provided between the active columns in a plurality of stacks, each stack extending lengthwise along the third direction, wherein the active columns, the charge-trapping material and the word line conductors together form a plurality of variable-threshold thin-film transistors, each variable-threshold thin-film transistor comprising an associated one of the word line conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the word line conductor, and the first and second heavily doped regions;
• first and second pluralities of interconnection conductors running lengthwise along the second direction above and beneath the active columns, respectively, wherein (i) the first heavily doped region forms a local bit line and serves as a first drain or source terminal of the variable-threshold thin-film transistor, the local bit line being selectably connected to an associated one of the second plurality of interconnection conductors, (ii) the associated word line conductor serves as a gate terminal to provide a control voltage to the variable-threshold thin-film transistor;
• and (iii) the second heavily doped region forms a local source line and serves as a second drain or source terminal of the variable-threshold thin-film transistor, the local source line being connected to an associated one of the first plurality of interconnection conductors.