Three-dimensional memory device having a buried source line extending to scribe line and method of making thereof

A method of forming a three-dimensional memory device, comprising:

• forming field effect transistors on a semiconductor substrate;
• forming at least one lower level dielectric layer and lower metal interconnect structures over the field effect transistors and over the semiconductor substrate;
• forming a buried source line over the at least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, wherein the buried source line comprises downward-protruding portions that are electrically connected to an upper portion of the semiconductor substrate;
• forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, wherein the sacrificial material layers are subsequently replaced with electrically conductive layers;
• forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate;
• forming memory stack structures in the memory openings, wherein each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel;
• and
• electrically isolating a portion of the buried source line that underlies the memory stack structures from the downward-protruding portions by laterally dividing the buried source line in a region between the memory stack structures and the downward-protruding portions,
• wherein:
• the memory openings are formed using an anisotropic etch process;
• and
• the downward-protruding portions conduct electrical charge between the buried source line and the semiconductor substrate during the anisotropic etch process.

A method of forming a three-dimensional memory device, comprising:

• forming at least one lower level dielectric layer over a semiconductor substrate;
• forming a buried source line over the at least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, wherein the buried source line comprises downward-protruding portions that are electrically connected to an upper portion of the semiconductor substrate;
• forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, wherein the sacrificial material layers are subsequently replaced with electrically conductive layers;
• forming memory openings through the alternating stack by an anisotropic etch process through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, wherein the downward-protruding portions conduct electrical charge between the buried source line and the semiconductor substrate during the anisotropic etch process;
• forming memory stack structures in the memory openings, wherein each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel;
• and
• removing portions of the at least one lower level dielectric layer and the alternating stack at a peripheral region of the semiconductor substrate, wherein a circumferential bevel region of the semiconductor substrate is physically exposed prior to the anisotropic etch process.