Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures

A vertical memory device structure comprising:

• a stack structure including alternating electrode layers and insulating layers extending from a cell array region of the device to a connection region of the device;
• a lower structure in the stack structure including an etch stop layer on an uppermost layer in the lower structure;
• an upper structure in the stack structure on the etch stop layer;
• a staircase structure defined by the upper and lower structures of the stack structure in the connection region;
• a vertical channel structure vertically penetrating through the upper and lower structures of the stack structure in the cell array region, the vertical channel structure having a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the etch stop layer;
• and
• a vertical dummy structure vertically penetrating through the staircase structure, the vertical dummy structure having a side wall with a planar profile at the level in the vertical dummy structure where the upper structure meets the etch stop layer and the planar profile extending into the upper structure and into the lower structure,
• wherein the etch stop layer is disposed in only the cell array region.

A vertical memory device structure comprising:

• a stack structure including alternating electrode layers and insulating layers extending from a cell array region of the device to a connection region of the device;
• a lower structure in the stack structure including one of the electrode layers or one of the insulating layers as an uppermost layer in the lower structure;
• an etch stop layer disposed on the uppermost layer in the lower structure
• an upper structure in the stack structure directly on the uppermost layer in the lower structure;
• a staircase structure defined by the upper and lower structures of the stack structure in the connection region;
• a vertical channel structure vertically penetrating through the upper and lower structures of the stack structure in the cell array region, the vertical channel structure having a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the uppermost layer in the lower structure;
• and
• a vertical dummy structure vertically penetrating through the staircase structure, the vertical dummy structure having a side wall with a planar profile at the level in the vertical dummy structure where the upper structure meets the uppermost layer in the lower structure, wherein a diameter of the vertical dummy structure gradually decreases from a top surface of the vertical dummy structure to a bottom surface of the vertical dummy structure,
• wherein the etch stop layer is disposed in only the cell array region.