Integrated structures containing vertically-stacked memory cells

An integrated structure comprising, along a cross-section:

• a stack of alternating dielectric levels comprising a dielectric material and conductive levels that comprise a conductive material that physically contacts the dielectric material;
• vertically-stacked memory cells within the conductive levels, the vertically-stacked memory cells comprising a charge trapping region and an insulative material within the conductive levels;
• an opening extending through the stack, the opening having a continuous vertical sidewall along the dielectric material and the insulative material;
• non-germanium-containing channel material liners along sidewalls of the opening and along the memory cells, the non-germanium-containing channel material liners being in direct contact with the dielectric material and the insulative material and comprising one or more members of the group consisting of silicon carbide, tin oxide, gallium arsenide, zinc oxide and indium oxide;
• germanium-containing channel material liners within the opening and along the non-germanium-containing material liners;
• and
• an insulator-filled hollow within the opening and between the germanium-containing liners.