Three-dimensional memory device including vertically offset drain select level layers and method of making thereof

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and stack level electrically conductive layers located over a top surface of a substrate;
• initial first drain select level electrically conductive layers and initial second drain select level electrically conductive layers that are vertically offset and located over the alternating stack, wherein the initial second drain select level electrically conductive layers are vertically offset from the initial first drain select level electrically conductive layers and are located in areas that do not overlap with the initial first drain select level electrically conductive layers in a plan view along a direction perpendicular to the top surface of the substrate;
• a first set of memory stack structures extending through the alternating stack and the initial first drain select level electrically conductive layers;
• and
• a second set of memory stack structure extending through the alternating stack and the initial second set of electrically conductive layers;
• wherein:
• each memory stack structure of the first and the second sets of memory stack structure comprises a vertical channel and a memory film;
• the stack level electrically conductive layers comprise horizontal word lines, wherein each word line contacts the first and the second set of memory stack structures and does not have vertically offset portions;
• the first set of memory stack structures directly contacts the initial first drain select level electrically conductive layers and does not directly contact the second drain select level electrically conductive layers;
• and
• the second set of memory stack structure directly contacts the initial second drain select level electrically conductive layers and does not directly contact the first drain select level electrically conductive layers.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and stack level electrically conductive layers located over a top surface of a substrate;
• initial first drain select level electrically conductive layers and initial second drain select level electrically conductive layers that are vertically offset and located over the alternating stack, wherein the initial second drain select level electrically conductive layers are vertically offset from the initial first drain select level electrically conductive layers and are located in areas that do not overlap with the initial first drain select level electrically conductive layers in a plan view along a direction perpendicular to the top surface of the substrate;
• a first set of memory stack structures extending through the alternating stack and the initial first drain select level electrically conductive layers;
• a second set of memory stack structure extending through the alternating stack and the initial second set of electrically conductive layers;
• additional first drain select level electrically conductive layers and additional second drain select level electrically conductive layers located vertically above the initial first drain select level electrically conductive lavers and the initial second drain select level electrically conductive layers;
• and
• insulating spacer layers located between each vertically neighboring pair of initial and additional first drain select level electrically conductive layers and between each vertically neighboring pair of initial and additional second drain select level electrically conductive layers, wherein each bottommost initial second drain select level electrically conductive layer is located above a first horizontal plane including top surfaces of bottommost initial first drain select level electrically conductive layers and below a topmost surface of an insulating spacer layer that contacts the initial bottommost first drain select level electrically conductive layers.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and stack level electrically conductive layers located over a top surface of a substrate;
• initial first drain select level electrically conductive lavers and initial second drain select level electrically conductive layers that are vertically offset and located over the alternating stack, wherein the initial second drain select level electrically conductive lavers are vertically offset from the initial first drain select level electrically conductive layers and are located in areas that do not overlap with the initial first drain select level electrically conductive layers in a plan view along a direction perpendicular to the top surface of the substrate;
• a first set of memory stack structures extending through the alternating stack and the initial first drain select level electrically conductive layers;
• and
• a second set of memory stack structure extending through the alternating stack and the initial second set of electrically conductive lavers;
• wherein:
• the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
• some of the stack level electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
• the substrate comprises a silicon substrate;
• the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
• at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
• the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
• the stack level electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, and the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;
• and
• the array of monolithic three-dimensional NAND strings comprises:
• a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
• a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.