Control gate dummy for word line uniformity and method for producing the same

A device comprising:

• a substrate having a memory cell (MCEL) region, a high voltage (HV) region and a logic region, separated by an isolation region;
• a plurality of control gate (CG) stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region with isolation region in-between;
• a first spacer and a second spacer on sidewalls of the plurality of CG stacks and the plurality of CG dummy stacks;
• an erase gate (EG) and a word line (WL) on the MCEL region, wherein the EG further comprises:
• a source region in the MCEL region of the Si substrate;
• and
• a silicon oxide over the source region;
• and
• a polysilicon layer within the EG, the WL and adjacent to the plurality of CG dummy stacks, wherein the polysilicon within the EG is coplanar with the polysilicon within the WL.

A method comprising:

• providing a silicon (Si) substrate having a memory cell (MCEL) region, a high voltage (HV) region and a logic region, respectively, separated by a shallow trench isolation (STI);
• forming a plurality of control gate (CG) stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively;
• forming a first polysilicon layer over the Si substrate;
• forming a spacer over portions of the first polysilicon layer over the HV region and the logic region;
• forming a second polysilicon layer over the first polysilicon layer and the spacer, an erase gate (EG) and a word line (WL) on the MCEL region formed, wherein forming the EG on the MCEL region comprises:
• forming a source region in the MCEL region of the Si substrate by an N-type dopant implant;
• and
• oxidizing an upper portion of the source region;
• planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks by chemical mechanical polishing (CMP);
• and
• removing portions of the second polysilicon layer in-between the plurality of CG stacks and adjacent to the plurality of CG dummy stacks by a polysilicon etch back (EB) process or reactive ion etching (RIE).