Non-volatile split game memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

A method of forming a memory device, comprising:

• providing a semiconductor substrate having a memory cell area, a core device area and a High Voltage (HV) device area;
• forming spaced apart source and drain regions in the memory cell area of the substrate, with a channel region extending between the source and drain regions;
• forming a conductive floating gate disposed over and insulated from a first portion of the channel region and a portion of the source region;
• forming a conductive control gate disposed over and insulated from the floating gate;
• forming a conductive erase gate disposed over and insulated from the source region;
• forming first insulation material over the erase gate;
• forming second insulation material over a surface portion of the substrate in the HV device area;
• forming a High-K Metal Gate (HKMG) layer that extends over the memory cell area, the core device area and the HV device area, wherein the HKMG layer includes:
• a layer of high K dielectric material, and
• a layer of metal material on the layer of high K dielectric material;
• forming a conductive layer that extends over the HKMG layer in the memory cell area, the core device area and the HV device area;
• removing portions of the HKMG layer and the conductive layer from the memory cell area, the core device area and the HV device area, wherein:
• a first portion of the HKMG layer and a first portion of the conductive layer disposed over a second portion of the channel region remain as a word line gate,
• a second portion of the HKMG layer and a second portion of the conductive layer remain in the core device area as a first logic gate, and
• a third portion of the HKMG layer and a third portion of the conductive layer remain in the HV device area as a second logic gate.