US 10,381,357 B2Granted

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

AssigneeMicron Technology, Inc.

InventorsKamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta

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Abstract

Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Claims6

Dependent claims

An apparatus, comprising:

a memory cell having two transistors and one capacitor;
the two transistors being a first transistor and a second transistor;
the capacitor having a first node coupled with a source/drain region of the first transistor, and having a second node coupled with a source/drain region of the second transistor;
the memory cell having a first body region vertically offset from the source/drain region of the first transistor, and having a second body region vertically offset from the source/drain region of the second transistor;
a first body connection line coupling the first body region of the memory cell to a first conductive region having a first reference voltage;
a second body connection line coupling the second body region of the memory cell to a second conductive region having a second reference voltage;
a wordline coupled with the first and second transistors of the memory cell;
the wordline including first and second gate regions of the first and second transistors, respectively;
the first and second gate regions being proximate the first and second body regions;
a segment of the wordline being between the first and second gate regions;
the memory cell and wordline being over an underlying supporting substrate;
the capacitor being vertically offset relative to the wordline;
and
wherein:
the capacitor is above the wordline;
the first gate region of the wordline has a first upper surface and a first lower surface;
the second gate region of the wordline has a second upper surface and a second lower surface;
the segment of the wordline has a third upper surface between the first and second upper surfaces of the first and second gate regions;
the segment of the wordline has a third lower surface between the first and second lower surfaces of the first and second gate regions;
the third upper surface is substantially planar with the first and second upper surfaces;
and
the third lower surface is vertically offset relative to the first and second lower surfaces.

19 more elements

An apparatus, comprising:

a first memory cell having two transistors and one capacitor;
the two transistors of the first memory cell being a first transistor and a second transistor;
the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions;
the capacitor of the first memory cell being a first capacitor;
the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor;
the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor;
a second memory cell having two transistors and one capacitor;
the two transistors of the second memory cell being a third transistor and a fourth transistor;
the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions;
the capacitor of the second memory cell being a second capacitor;
the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor;
the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor;
a first body connection line coupling the first body region of the first memory cell and the third body region of the second memory cell to a first reference voltage;
a second body connection line coupling the second body region of the first memory cell and the fourth body region of the second memory cell to a second reference voltage;
wherein the first and second memory cells share a digit line;
and wherein the digit line includes a first comparative bitline coupled to the second source/drain region of the first transistor and the sixth source/drain region of the third transistor, and includes a second comparative bitline coupled to the fourth source/drain region of the second transistor and the eighth source/drain region of the fourth transistor;
and
wherein:
a first wordline is coupled with the first and second transistors of the first memory cell;
and
a second wordline is coupled with the third and fourth transistors of the second memory cell.

18 more elements

An apparatus, comprising:

a first memory cell having two transistors and one capacitor;
the two transistors of the first memory cell being a first transistor and a second transistor;
the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions;
the capacitor of the first memory cell being a first capacitor;
the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor;
the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor;
a second memory cell having two transistors and one capacitor;
the two transistors of the second memory cell being a third transistor and a fourth transistor;
the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions;
the capacitor of the second memory cell being a second capacitor;
the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor;
the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor;
a first body connection line coupling the first body region of the first memory cell and the third body region of the second memory cell to a first reference voltage;
a second body connection line coupling the second body region of the first memory cell and the fourth body region of the second memory cell to a second reference voltage;
wherein the first and second memory cells share a digit line;
and wherein the digit line includes a first comparative bitline coupled to the second source/drain region of the first transistor and the sixth source/drain region of the third transistor, and includes a second comparative bitline coupled to the fourth source/drain region of the second transistor and the eighth source/drain region of the fourth transistor;
and
wherein the first and second body connection lines are doped to a first conductivity type, and are spaced from the first and second comparative bitlines by spacing regions comprising semiconductor material doped to a second conductivity type different from the first conductivity type;
said spacing regions comprising the second, fourth, sixth and eighth source/drain regions.

16 more elements

An apparatus, comprising:

a first memory cell having two transistors and one capacitor;
the two transistors of the first memory cell being a first transistor and a second transistor;
the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions;
the capacitor of the first memory cell being a first capacitor;
the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor;
the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor;
a second memory cell having two transistors and one capacitor;
the two transistors of the second memory cell being a third transistor and a fourth transistor;
the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions;
the capacitor of the second memory cell being a second capacitor;
the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor;
the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor;
the second memory cell sharing first and second comparative bitlines with the first memory cell;
a first body connection line coupling the first body region of the first memory cell to a first reference voltage;
a second body connection line coupling the second body region of the first memory cell to a second reference voltage;
a third body connection line coupling the third body region of the second memory cell to a third reference voltage;
a fourth body connection line coupling the fourth body region of the second memory cell to a fourth reference voltage;
and
wherein the first and third body connection lines are substantially parallel to the first comparative bitline;
wherein the second and fourth body connection lines are substantially parallel to the second comparative bitline;
and wherein the first, second, third and fourth body connection lines comprise conductively-doped semiconductor material.

18 more elements

An apparatus, comprising:

a first memory cell having two transistors and one capacitor;
the two transistors of the first memory cell being a first transistor and a second transistor;
the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions;
the capacitor of the first memory cell being a first capacitor;
the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor;
the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor;
a second memory cell having two transistors and one capacitor;
the two transistors of the second memory cell being a third transistor and a fourth transistor;
the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions;
the capacitor of the second memory cell being a second capacitor;
the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor;
the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor;
the second memory cell sharing first and second comparative bitlines with the first memory cell;
a first body connection line coupling the first body region of the first memory cell to a first reference voltage;
a second body connection line coupling the second body region of the first memory cell to a second reference voltage;
a third body connection line coupling the third body region of the second memory cell to a third reference voltage;
a fourth body connection line coupling the fourth body region of the second memory cell to a fourth reference voltage;
wherein the first and second comparative bitlines comprise metal;
and
wherein the first, second, third and fourth body connection lines are doped to a first conductivity type, and are spaced from the first and second comparative bitlines by spacing regions comprising semiconductor material doped to a second conductivity type different from the first conductivity type;
said spacing regions comprising the second, fourth, sixth and eighth source/drain regions.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/043,653Filed 24 Jul 2018 · us provisional application
Priority: 31 Aug 2017
Published: US 2019/0067298 A128 Feb 2019
Granted: 13 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

G11C 11/401
Using transistors: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
H10B 20/40
ROM only: having the source region and drain region on different levels, e.g. vertical channel
G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…
G11C 11/408
For memory cells of the field-effect type: address circuits