Low power embedded one-time programmable (OTP) structures

A device comprising:

• a semiconductor substrate;
• an isolation layer disposed on the substrate;
• a memory region defined on the substrate, the memory region including a one-time programmable memory cell, and the one-time programmable memory cell comprises comprising:
• a first semiconductor fin disposed on the semiconductor substrate, the first semiconductor fin having a lower portion surrounded by the isolation layer and an upper portion protruding above the isolation layer, and the upper portion of the first semiconductor fin having a sharpened tip profile, and
• a first gate disposed on the isolation layer and extending laterally to traverse the first semiconductor fin, the first gate including a gate electrode layer and a gate dielectric layer that are arranged in part over the sharpened tip profile of the upper portion of the first semiconductor fin;
• and
• a logic region defined on the substrate, the logic region including a logic transistor, and the logic transistor comprising:
• a second semiconductor fin disposed on the substrate, the second semiconductor fin including a lower portion surrounded by the isolation layer and an upper portion protruding above the isolation layer, and the upper portion of the second semiconductor fin having a rectangular-shaped cross-section with a substantially planar top surface, and
• logic a second gate disposed on the isolation layer and extending laterally to traverse the second semiconductor fin, and the second gate including a second gate electrode layer and a gate dielectric layer that are arranged in part over the planar top surface of the upper portion of the second semiconductor fin, and
• wherein the first gate dielectric layer over the sharpened tip profile of the upper portion of the first semiconductor fin has a breakdown voltage that is less than a breakdown voltage of the second gate dielectric layer over the substantially planar top surface of the second semiconductor fin.